System and Method for Adaptively Allocating Resources in a Transcoder

ABSTRACT

An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional of and claims priority to U.S. patentapplication Ser. No. 12/564,532 filed on Sep. 22, 2009. Said applicationincorporated by reference for all purposes.

TECHNICAL FIELD

The technical field relates in general to communications, and, morespecifically, the system and method for allocating processing resourcesin a media gateway that deals with video transcoding (i.e., a videomedia gateway).

BACKGROUND

It is often necessary in a video communication system to translatesignals between various formats. For example, it may be necessary totranslate a signal encoded in H.264 into a signal encoded in MPEG-4. Inorder to accomplish this, a transcoding gateways application (i.e., atranscoder) can be provided.

A media gateway often contains multiple channels, each of which cantranslate a video stream from one format to another. Typically thegateway receives video streams over IP networks, transcodes the contentand sends the transcoded media on IP network. These channels each bufferincoming packets, decode the packets from one format, and then re-encodethem into a second format for transmission. However, due to the burstynature of signal traffic it can be difficult to allocate resources inthe media gateway efficiently among the channels.

Encoding is typically more resource-intensive then decoding. Inpractical terms that means that an encoder takes a greater amount ofMIPS (i.e., million instructions per second) as compared to a decoder.As a result, when incoming packets are buffered in a transcodingchannel, the encoder typically governs the drain rate of the buffer onthe decoder leg.

When consecutive frames are consuming a higher than average/median MIPSbudget, the input buffer will begin to fill faster than it drains. If itreaches its maximum level, then frames will have to be dropped fordecoding. This can cause problems with decoding, since video decoding isoften heavily reliant upon information from adjacent packets. Thus, whenpackets are dropped, decoding quality can drop dramatically.

One way to ensure adequate decoding resources for each channel would beto provide processing for each channel sufficient to meet a worst-casescenario (i.e., a worst-case MIPS load for the channel). However, usingsuch a system can be very wasteful, since in a worst-case each channelcan demand a great deal of resources. Because this would require eachchannel to be allocated resources based on a worst-case, during mostnormal operation such channels would have a large amount of unusedprocessing capacity going to waste.

It would therefore be desirable to provide an adaptive transcoder thatcan allocate its resources as needed when channels become congested. Itwould further be desirable to provide a transcoder that can account forsituations in which all available channels are congested at the sametime, and can limit image processing and encoding operations, whilecontinuing to allow the decoding operation to use as much of theprocessing resources as it requires.

SUMMARY

Embodiments described herein provide a system and method for adaptivelyallocating resources in a media gateway kind of solution. In particular,they provide a way for offloading part of processing to a differentprocessing core if a buffer drain rate falls too far behind the bufferfill rate. They also allow for a reduction in image processing (such asoptionally turn off image denoising, sharpening etc functionalitybetween decoder and encoder) and encoding demand by shutting off certainencoding features (and thus reduce MIPS consumption on the encoder) toincrease the buffer drain rate.

Accordingly, a first disclosed embodiment described herein provides anadaptive transcoder, comprising: a shared memory containing a pluralityof decoder buffers (e.g., FIFOs) configured to store a plurality ofincoming data packets, a plurality of decoder instances configured tocontrol a decoding process to generate a plurality of image raw databased on the plurality of incoming data packets, and a plurality ofencoder instances configured to control an encoding process to generatea plurality of outgoing packets based on the image raw data; and a dataprocessing element containing a plurality of processing cores and a corecontroller. Each of the plurality of decoder instances is paired withone of the plurality of encoder instances, and each of the decoderbuffers (FIFOs) is associated with one of the decoder instances. Eachrespective decoder buffer (FIFO) includes a respective monitoringelement for monitoring a status of each the respective decoder buffer,and providing buffer data corresponding to the status of the respectivedecoder buffer. Each of the plurality of the encoder instances isassociated with a corresponding one of the plurality of processingcores. The core controller uses the buffer data to associate each of theplurality of decoder instances with a selected one of the plurality ofprocessing cores.

A second disclosed embodiment described herein provides a method ofadaptively controlling decoding and encoding in a transcoder,comprising: receiving incoming data packets; storing the incoming datapackets in a memory element; determining an amount of the memory elementcurrently being used to store the incoming data packets; allocatingprocessing resources for encoding and decoding based on the amount ofthe memory element currently being used; performing a decoding operationon the incoming data packets to generate image raw data; and performingan encoding operation on the image raw data to generate outgoingpackets.

A third disclosed embodiment described herein provides An adaptivetranscoder, comprising: a shared memory containing a channel instanceconfigured to provide instructions and memory for translating aplurality of incoming data packets from a first format to a secondformat; and a data processing element configured to provide the dataprocessing for translating the plurality of incoming data packets fromthe first format to the second format. The channel instance includes adecoder FIFO buffer configured to store the plurality of incoming datapackets, and to provide FIFO data indicating how many packets arecontained in the FIFO buffer, a decoder instance configured to control adecoding process from the first format to generate a plurality of imageraw data based on the plurality of incoming data packets, and an encoderinstance configured to control an encoding process to generate aplurality of outgoing packets in the second format based on the imageraw data. The data processing element includes a plurality of processingcores, each configured to perform the decoding process based on thedecoder instance, or the encoding process based on the encoder instance,and a core controller is configured to assign of the decoder instanceone of the plurality of processing cores.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying figures, where like reference numerals refer toidentical or functionally similar elements and which together with thedetailed description below are incorporated in and form part of thespecification, serve to further illustrate various exemplary embodimentsand to explain various principles and advantages in accordance with theembodiments.

FIG. 1 is a functional block diagram of a transcoder according todisclosed embodiments;

FIG. 2 is an alternate block diagram of the transcoder according todisclosed embodiments;

FIG. 3 is a block diagram of the shared memory of FIGS. 1 and 2according to disclosed embodiments;

FIG. 4 is a block diagram of a channel instance of FIG. 3 according todisclosed embodiments;

FIG. 5 is a block diagram of a decoder FIFO of FIG. 4 according todisclosed embodiments;

FIG. 6 is a block diagram showing a default resource allocationaccording to disclosed embodiments;

FIG. 7 is a block diagram showing a revised resource allocationaccording to disclosed embodiments;

FIG. 8 is a flowchart illustrating a transcoding operation, includingresource allocation, according to disclosed embodiments; and

FIG. 9 is a flowchart illustrating an operation of transcoding resourceallocation for a single channel according to disclosed embodiments.

DETAILED DESCRIPTION

In overview, the present disclosure concerns a system and method foradaptively allocating resources in a media gateway. More specifically,it relates to a circuit and related method for using an indicator of howfull a decoding packet buffer is to determine how resources should beallocated in the transcoder. The congestion in the decoding packetbuffer provides a good indicator of the congestion of the associatedchannel and allows the controller to more accurately allocate transcoderresources, and potentially limit encoding parameters to reducecongestion on the individual channels.

The instant disclosure is provided to further explain in an enablingfashion the best modes of performing one or more embodiments. Thedisclosure is further offered to enhance an understanding andappreciation for the inventive principles and advantages thereof, ratherthan to limit in any manner the invention. The invention is definedsolely by the appended claims including any amendments made during thependency of this application and all equivalents of those claims asissued.

It is further understood that the use of relational terms such as firstand second, and the like, if any, are used solely to distinguish onefrom another entity, item, or action without necessarily requiring orimplying any actual such relationship or order between such entities,items or actions. It is noted that some embodiments may include aplurality of processes or steps, which can be performed in any order,unless expressly and necessarily limited to a particular order; i.e.,processes or steps that are not so limited may be performed in anyorder.

Much of the inventive functionality and many of the inventive principleswhen implemented, are best supported with or in software or integratedcircuits (ICs), such as a digital signal processor and softwaretherefore, and/or application specific ICs. It is expected that one ofordinary skill, notwithstanding possibly significant effort and manydesign choices motivated by, for example, available time, currenttechnology, and economic considerations, when guided by the concepts andprinciples disclosed herein will be readily capable of generating suchsoftware instructions or ICs with minimal experimentation. Therefore, inthe interest of brevity and minimization of any risk of obscuringprinciples and concepts, further discussion of such software and ICs, ifany, will be limited to the essentials with respect to the principlesand concepts used by the exemplary embodiments.

Transcoding Circuit

A multiple-channel transcoding circuit is provided that receivesincoming packets (i.e., frames) and translates them from one format intoanother. FIG. 1 is a functional block diagram of a transcoder 100according to disclosed embodiments. As shown in FIG. 1, the transcoder100 includes an input processing element 110, a shared memory 120, adata processing element 130, and an output processing element 140element. The data processing element 130 further includes a decoder 150,an image processor 160, and an encoder 170.

The input processing element 110 receives an incoming channel signal,and performs one or more processing operations on the incoming signal toextract incoming packets (i.e., frames). These processing operations caninclude packet extraction, application, filtering, and the like.

The shared memory 120 receives the incoming packets from the inputprocessing element, stores them, and serves as a memory element foroperations performed by the data processing element 130. It can be anykind of suitable dynamic memory, e.g., RAM, flash memory, and the like.

The shared memory 120 includes a plurality of FIFO buffers, one for eachchannel. It monitors the status of these FIFO buffers and provides FIFOdata to the data processing element 130 regarding the status of theseFIFO buffers. In particular, the FIFO data can include informationregarding how full each of the FIFO buffers is (i.e., how many packetseach FIFO buffer contains or how close each FIFO buffer is beingcompletely full).

The data processing element 130 performs the actual decoding, imageprocessing, and encoding operations of the transcoding circuit.Functionally, it includes the decoder 150, the image processor 160, andthe encoder 170. However, its actual implementation may vary. In someembodiments it may include separate dedicated devices for decoding,image processing, and encoding. In other embodiments it can includemultiple processing devices (e.g., central processing units orprocessing cores) that can perform one or more of the required decoding,image processing, or encoding operations. In such an embodiment ofprocessing devices can be assigned as needed to perform these variousoperations.

The data processing element 130 operates based on state machineinformation contained in the shared memory 120, based on the FIFO data,and based on image data (e.g., the incoming packets) stored in theshared memory 120. It may have some internal memory, but also reads andwrites raw image data to and from the shared memory. In this waydifferent portions of the data processing element 130 may operate on thesame data along a transcoding path.

The decoder 150 performs a decoding operation on an incoming packetbased on state machine information and FIFO data received from theshared memory 120 to transform incoming packets from a first format intoimage raw data suitable for image processing and encoding. The decoder150 reads the packet data from the shared memory 120, and stores thedecoded image raw data to the shared memory 120.

The image processor 160 performs one or more image processing operationson the image raw data based on state machine information and FIFO datareceived from the shared memory 120 to generate modified image raw data.These can include de-blocking, quarter PEL interpolation, 8×8 MV, Intra4×4 and the like. The image processor 160 reads the image raw data fromthe shared memory 120 and stores the modified image raw data to theshared memory 120.

The encoder 170 performs an encoding operation on the modified image rawdata based on state machine information and FIFO data received from theshared memory 120 to generate outgoing packets (i.e., frames) in asecond format. The encoder 160 reads the modified image raw data fromthe shared memory 120 and provides the outgoing packets to be outputprocessing element 140.

The output processing element 140 receives the outgoing packets from theencoder 170 in the data processing element 130, performs one or moresignal processing operations, and provides the outgoing packets as anoutgoing channel signal. These signal processing operations can includeback and processing, filtering, application, aggregation, etc.

FIG. 2 is an alternate block diagram of the transcoder 200 according todisclosed embodiments. FIG. 2 is similar to FIG. 1, but shows aparticular implementation of the data processing element 230.

As shown in FIG. 2, the transcoder 200 includes an input processingelement 110, a shared memory 120, a data processing element 230, and anoutput processing element 140. The data processing element 130 furtherincludes a plurality of cores 210A, 210B, 210C, . . . , 210D (generallyreferred to as cores 210), and a controller 220. Elements in FIG. 2 thatare the same as those in FIG. 1 will not be described. Only elementsthat are different in FIG. 2 will be described.

The shared memory 120 generates FIFO data and sends and receivesoperational signals. The FIFO data is as described with respect to FIG.1, and the operational signals can include the packet data the image rawdata, the modified image raw data, and the state machine information.

The cores 210 are processing elements (e.g., central processing units,microprocessors, or the like.) that are capable of performing thedecoding, image processing, and encoding operations. They each receivethe FIFO data and appropriate operational signals from the shared memory120, and are capable of storing operational signals into the sharedmemory. For example when a core 210 operates as a decoder it receivesthe FIFO data, the packet data, and the state machine informationrelating to decoding from the shared memory 120, and stores the imageraw data to the shared memory 120. Each of the cores 210 also receivesassignment data from the controller 220, which identifies the core thatwill perform each operation.

In the disclosed embodiments, image processing and encoding operationsare performed by the same core 210. However, this is merely by way ofexample. In alternate embodiments image processing could be associatedwith the core 210 that performs decoding, or it could be separatelyassigned, independent which core 210 performs decoding which core 210performs encoding.

The controller 220 uses the FIFO data to generate the assignment data.In the disclosed embodiments, each operation (i.e., decoding, imageprocessing, and encoding) has a default core that it will be assignedto. For example if the number of cores 210 is equal to the number ofchannels each set of associated decoding, image processing, and encodingoperations will be assigned to one core 210. If there are fewer cores210 then channels, or more cores 210 then channels, then a different setof default assignments can be arranged to spread out processing amongthe cores 210. However, generally all of the operations for a givenchannel will by default be assigned to the same core. In alternateembodiments, however, a truly dynamic assignment approach can be used inwhich one or more operations are dynamically assigned at each instancebased on channel congestion.

As noted above, at times data traffic on a particular channel will behigh, requiring greater system resources for processing that channel(e.g., typically requiring more MIPS for encoding). In such acircumstance, it is desirable to either shift processing to differentcore 210, or limit the processing resources used by the core 210 forprocessing the channel. Therefore, the controller 220 also uses the FIFOdata to determine when a channel has become congested and should havesome of its operations assigned to a different core 210.

The controller 220 uses the FIFO data from FIFO buffers associated witheach channel to determine both when processing should be shifted to adifferent core 210, and whether there is a core 210 with sufficient freeresources to handle the reassigned processing.

Because all of the image processing data (e.g. packet data, image rawdata, and modified image raw data) are stored in the shared memory 120,it is possible for the processing of a channel to be performed bydifferent cores 210. For example, core 0 210A may be assigned to performa decoding operation, and core 1 210B may be assigned to perform animage processing/encoding operation. But the fact that they are separatecores 210 will not interfere with their operation. The core 0 210A willread the packet data from the shared memory 120, perform its decodingoperation to generate image raw data, and will store the image raw datato the shared memory 120. The core 1 210B will then read the image rawdata from the shared memory 120, perform image processing on the imageraw data to generate modified image raw data, and will perform anencoding operation on the modified image raw data to generate theoutgoing packets.

FIG. 3 is a block diagram of the shared memory 120 of FIGS. 1 and 2according to disclosed embodiments. As shown in the FIG. 3, the sharedmemory 120 includes a plurality of channel instances 310A, 310B, 310C, .. . , 310D (generally referred to as channel instances 310). Each ofthese channel instances 310 can receive incoming data packets from theprocessing element, and store them in an associated FIFO buffer. Thechannel instances 310 also contain both the state machine informationand ability to store image data necessary to perform a particulartranscoding operation. For example, each channel instance may providefor different translation from one format to another. Alternatively,multiple channels may be provided for particularly popular transcodingoperations.

The channel instances 310 each provide operational signals and FIFO datanecessary for performing associated decoding, image processing, andencoding operations, and are capable of receiving and storingoperational signals from the data processing element 130.

FIG. 4 is a block diagram of a channel instance of FIG. 3 according todisclosed embodiments. As shown in FIG. 4, a channel instance 310includes a decoder FIFO 410, a decoder instance 420, an image processinstance 440, and an encoder instance 450.

The decoder FIFO 410 is a buffer that allows for the storage of acertain number of packets for decoding. It can output the packets aspart of the operational signals, and can also output the FIFO signalsindicating a status of the decoder FIFO 410.

The decoder instance 420 includes the necessary state machineinformation for performing the associated decoding operation, as well aseither dedicated memory for storing associated image raw data, orinformation identifying how common memory in the shared memory 120 maybe accessed to store image data.

The image process instance 440 includes the necessary state machineinformation for performing the associated image processing operation, aswell as either dedicated memory for storing associated image raw data,or information identifying how common memory in the shared memory 120may be accessed to store image data.

The encoder instance 450 includes the necessary state machineinformation for performing the associated encoding operation, as well aseither dedicated memory for storing associated image raw data, orinformation identifying how common memory in the shared memory 120 maybe accessed to store image data.

FIG. 5 is a block diagram of a decoder FIFO of FIG. 4 according todisclosed embodiments. As shown in FIG. 5, the decoder FIFO 410 includesa plurality of register elements 510 and a monitoring element 520.

The register elements 510 may each contain one packet of incoming data.The decoder FIFO 410 includes a set number of register elements 510(i.e., Z elements in the disclosed embodiment). The decoder FIFO is afirst in-first out buffer, meaning that packets are output in the orderin which they are input.

The monitoring element 520 monitors the status of the register elements510 determine how many of them are filled with packet data forprocessing. It provides FIFO data that includes a FIFO identifieridentifying the decoder FIFO/channel, a warning signal that indicateswhen X register elements 510 are filled with packet data, an alertsignal that indicates when Y register elements 510 are filled withpacket data, and a critical alert signal that indicates when Z registerelements 510 are filled with packet data (where Z>Y>X).

In the disclosed embodiments Z is equal to the total number of registerelements 510 in the decoder FIFO 410. However, in alternate embodimentsZ could be less than the total number of register elements 510. In suchembodiments, the critical alert signal will become active before thedecoder FIFO 410 was completely filled. In addition, while in thedisclosed embodiment three signals are provided indicating whether theregister has filled to three different thresholds, more or fewer signalscould be used identifying whether the number of registers in the decoderFIFO 410 has passed a different number of thresholds.

FIG. 6 is a block diagram showing a default resource allocationaccording to disclosed embodiments; and FIG. 7 is a block diagramshowing a revised resource allocation according to disclosedembodiments.

As shown by way of example in FIGS. 6 and 7, a transcoder 600 includes Mchannel instances 310A, 310B, . . . , 310D and N cores 210A, 210B, . . ., 210D. Channel instance 0 310A includes decoder instance 0 420A andencoder instance 0 450A; channel instance 1 310B includes decoderinstance 1 420B and encoder instance 1 450B; and channel instance M 310Dincludes decoder instance M 420D and encoder instance M 450D.

In a default resource allocation for the transcoder 600 (See FIG. 6),decoder instance 0 420A and encoder instance 0 450A are both assigned tocore 0 210A, decoder instance 1 420B and encoder instance 1 450B areboth assigned to core 1; and decoder instance M 420D and encoderinstance M 450D are both assigned to core N 210D. Thus, in a defaultposition each core 210 handles the decoding/coding four a given channelinstance 310.

FIG. 7 shows a revised resource allocation when the Mth channel instance310D becomes too congested after the receipt of a new packet, but thefirst channel instance 310B is not congested. In this case, the decoderinstance M 420D is reassigned from core N 210D to core 1 210B, while theencoder instance 450D remains associated with core N 210D.

This assignment will remain until the channel instance M receives a newpacket, at which time the controller 220 in the data processing element130 will again assess how elements within each channel instance 410should be assigned. In this way, the resources in the data processingelement 130 of the transcoder 100, 200 can be dynamically assigned basedon a determination of current channel congestion.

Method of Transcoder Optimization

FIG. 8 is a flowchart illustrating a transcoding operation, includingresource allocation, according to disclosed embodiments.

As shown in FIG. 8, the operation begins when the transcoder receives astream of packets (i.e., frames). (810) In various embodiments thisreception can be wired or wireless.

The transcoder then performs some input processing of received packets.(820) this can include packet extraction, filtering, amplification, orthe like. In some alternate embodiments however, this input processingmay be eliminated.

Once it has received and processed the incoming packets, the transcoderstores the incoming packets in the shared memory. (830) In the disclosedembodiments, the shared memory includes a plurality of decoder FIFObuffers that store the incoming packets.

The transcoder then determines the amount of memory used to store theincoming packets. (840) This operation is performed separately for eachchannel in order to estimate a level of congestion for eachcorresponding channel. In various disclosed embodiments this can includeproviding an indication of multiple levels of congestion. For example,the shared memory could indicate that a portion of the shared memorydedicated to a given channel has no congestion (i.e., it stores a numberof packets below a first threshold), has little congestion (i.e., itstores a number of packets between the first threshold and a secondthreshold), has a moderate amount of congestion (i.e., it stores anumber of packets between the second threshold and a third threshold),or has a large amount of congestion (i.e., it stores the number ofpackets between the third threshold and a fourth threshold). However,alternate embodiments can use more or fewer range categories. In someembodiments an indication of the highest congestion can represent a fullbuffer; in others it can represent a buffer nearing a full state.

Once the transcoder has determined the amount of memory used, itproceeds to determine which cores will be assigned for coding and whichcores will be assigned for decoding. (850) In disclosed embodiments adefault position is that the same core will be used for both decodingand coding in the same channel. Only when the channel becomes congestedwill the coding and decoding operations be split among separate cores.For example, if the determination of the amount of memory used aboveindicates no congestion in the channel, the same core will be used fordecoding and coding. If however, a higher level of congestion isdetermined for a channel, and a channel exists with a lower level ofcongestion, the transcoder may distribute coding and decoding operationsamong the available cores in a more even manner.

In general, the transfer of coding and decoding from core to core willonly be done on a packet by packet basis. Even though packets willtypically be broken up into smaller components for processing by thecores, it will generally be more efficient to have a single core processall of the components that make up a given packet.

Once the transcoder has determined which cores will perform the decodingand coding operations, it proceeds to determine what the imageprocessing and coding parameters will be for the encoding operations inthe various channels based on the determination of the amount of memoryused. (860) If there is a very high level of congestion (i.e., a channelmemory in the shared memory is storing a larger number of packets), thiscan indicate that all of the channels are increased in congestion. As aresult it may be necessary to alter either the image processing orencoding parameters to be less intensive in their use of core resources(e.g., MIPS). This can be achieved by either reducing the amount ofimage processing performed between decoding and encoding in thetranscoder, or by dropping packets during the encoding process.

In the disclosed embodiments, when the use of the decoder memory reachesa moderate threshold, above the low threshold, and amount of imageprocessing is reduced to limit the transcoding processes need for coreresources. And when the use of the decoder memory reaches a highthreshold, the transcoder begins to drop packets during encoding.

The disclosed transcoder does not drop packets for decoding, sincedecoding often relies on information from a previous packet to assist indecoding a current packet. However in any embodiments in which droppingpackets for decoding would not be detrimental to the decoding process,it would be possible to drop decoding packets as well.

Then, once the cores have been assigned and all of the parameters forencoding and decoding have been determined, the transcoder performsdecoding, image processing, and encoding in accordance with thoseparameters. (870)

Finally, the transcoder performs any necessary output processing on thepackets generated during this transcoding process (880), and outputs thepackets (890).

FIG. 9 is a flowchart illustrating an operation of transcoding resourceallocation for a single channel according to disclosed embodiments. Asshown in FIG. 9, processing begins when the transcoder receives a packetof data. (905) As noted above, this process will be performed for eachindividual channel.

Once received, the packet data will be stored into a channel FIFO. (910)A separate channel FIFO will be associated with each channel. This FIFOwill be associated with decoding operation, and can also be called thedecoder FIFO.

The transcoder will then determine whether a warning signal is activewith respect to the channel FIFO. (915) In the disclosed embodiments thewarning signal is active when the number of packets stored in thechannel FIFO rises to a first threshold value.

If the warning signal is not active, then the channel is not consideredcongested and the transcoder processes the packet in a default coreusing default image processing and coding parameters. (920) In thiscase, the load on the assigned core is considered to be low enough toallow full processing.

If however the warning signal is active, then the channel FIFO containsat least a number of packets equal to the first threshold value. Thetranscoder must then determine whether the alert signal is active. (925)In the disclosed embodiments the alert signal is active when the numberof packets stored in the channel FIFO is between the first thresholdvalue and a second threshold value (where the second threshold value isgreater than the first threshold value).

If the alert signal is not active, then the channel is consideredlightly congested. The transcoder then checks congestion for the otheravailable cores. (930) This check is made to determine whether any othercore has a low enough level of congestion to take on the decoding forthe channel. In some embodiments a core may be considered available ifit has a low level of congestion (i.e., it does not have a warningsignal active). Alternate embodiments can set different criteria,however.

Based on this congestion information, the transcoder determines whetheran alternate core is available for processing. (935)

If there is an alternate core available, the packet will be processed inthe alternate core. (940) If, however there is no alternate coreavailable (i.e., all other cores have levels of congestion too high toallow packets to be rerouted to them), the packet will be processed inthe default core. But the core must determine what level of processingit should apply.

If the alert signal is active, then the channel FIFO contains at least anumber of packets equal to the second threshold value. The transcoderwill then adjust processing parameters to reduce the load on the coreprocessing load (945). This adjustment of processing parameters caninclude revising or eliminating de-blocking, quarter PEL interpolation,8×8 MV, Intra 4×4 or the like.

The transcoder must then determine whether the critical alert signal isactive. (950) If the disclosed embodiments the critical alert signal isnot active then the channel is considered moderately congested. In thiscase, the number of packets stored in the channel FIFO is between thesecond threshold value and a third threshold value (where the thirdthreshold value is greater than the second threshold value). In such acase the adjustment of processing parameters should be sufficient toreduce the load on the cores, and the packet will be processed in adefault core using the adjusted processing parameters.

If, however, the critical alert signal is active, then the channel isconsidered highly congested. In this case the number of packets storedin the channel is at least at the third threshold. At this point theadjustment of processing parameters is not sufficient to reduce the loadon the cores. Therefore, the transcoder will begin skipping framesduring an encoding process (955), and the packet will be processed inthe default core (920).

This process will be repeated for each packet received in a givenchannel, and will be repeated for each channel. As noted above, althoughthe cores may break packets up into smaller pieces to process them thedetermination of how to dynamically allocate resources in the transcoderwill be performed at the packet boundaries of the incoming packets.

In this way, the processing resources in the transcoder (e.g., theprocessing ability of the transcoder's cores) can be dynamicallyallocated based on an estimate of the congestion of each channel in thetranscoder. The allocation process can begin by spreading out processingfrom busier cores to less busy cores. If that isn't sufficient, theamount of image processing can be reduced to lessen the load on thecores. Finally, if even that is not enough, packets can be dropped atthe encoding and the transcoder to further lessen the load of the cores.This allows the transcoder to more efficiently use its processingresources. And it allows that even in cases where there is temporaryhigh demand for processing resources, the transcoder will maintain anacceptable quality of service on all channels.

CONCLUSION

This disclosure is intended to explain how to fashion and useembodiments in accordance with the invention rather than to limit thetrue, intended, and fair scope and spirit thereof. The invention isdefined solely by the appended claims, as they may be amended during thependency of this application for patent, and all equivalents thereof.The foregoing description is not intended to be exhaustive or to limitthe invention to the precise form disclosed. Modifications or variationsare possible in light of the above teachings. The embodiment(s) waschosen and described to provide the best illustration of the principlesof the invention and its practical application, and to enable one ofordinary skill in the art to utilize the invention in variousembodiments and with various modifications as are suited to theparticular use contemplated. All such modifications and variations arewithin the scope of the invention as determined by the appended claims,as may be amended during the pendency of this application for patent,and all equivalents thereof, when interpreted in accordance with thebreadth to which they are fairly, legally, and equitably entitled.

1.-14. (canceled)
 15. An adaptive transcoder, comprising: a sharedmemory containing a channel instance configured to provide instructionsand memory for translating a plurality of incoming data packets from afirst format to a second format; and a data processing elementconfigured to provide the data processing for translating the pluralityof incoming data packets from the first format to the second format,wherein the channel instance includes a decoder FIFO buffer configuredto store the plurality of incoming data packets, and to provide FIFOdata indicating how many packets are contained in the FIFO buffer andindicators of the status of the FIFO Buffer, a decoder instanceconfigured to control a decoding process from the first format togenerate a plurality of image raw data based on the plurality ofincoming data packets, and an encoder instance configured to control anencoding process to generate a plurality of outgoing packets in thesecond format based on the image raw data, wherein the data processingelement includes a plurality of processing cores, each configured toperform the decoding process based on the decoder instance, or theencoding process based on the encoder instance, and a core controller isconfigured to assign of the decoder instance one of the plurality ofprocessing cores.
 16. The adaptive transcoder of claim 15, wherein theFIFO data indicators includes: a warning indicator indicating whetherthe FIFO buffer has reached a first threshold of stored packets; analert indicator indicating whether the FIFO buffer has reached a secondthreshold of stored packets, the second threshold being greater than thefirst threshold; and a critical alert indicator indicating whether theFIFO buffer has reached a third threshold of stored packets, the thirdthreshold being greater than the second threshold.
 17. The adaptivetranscoder of claim 16, wherein the core controller is configured toassign the FIFO buffer and the decoder instance to the one of theplurality of processing cores of based on a value of the warningindicator.
 18. The adaptive transcoder of claim 16, wherein the corecontroller is configured to control the encoding process to drop packetsduring encoding when the critical alert indicator indicates that therespective decoder buffer has reached the third threshold of storedpackets.
 19. The adaptive transcoder of claim 16, wherein the channelinstance further comprises an image processor instance configured toperform image processing operations on the image raw data after thedecoding process and before the encoding processor, and wherein theimage processor instance is configured to reduce the amount of imageprocessing performed during the image processing operations when thealert indicator indicates that the respective decoder buffer has reachedthe second threshold of stored packets.
 20. The adaptive transcoder ofclaim 0, wherein the shared memory further comprises a plurality ofchannel instances.